The present disclosure relates generally to improving the efficiency of a computer system for performing optical proximity correction (OPC). To improve the efficiency of a computer system for OPC, embodiments of the present disclosure can automatically create a minimal (i.e., lowest acceptable) size sample plan for optical proximity correction from an integrated circuit (IC) layout. The created sample plan may be composed of one or more portions of the IC layout known as “clips.” More specifically, the present disclosure relates to methods, program products, and systems which can create a sample plan based on whether a projected sample plan with a candidate clip would provide significant additional relevancy and coverage of the sampled IC layout.
As IC components have continued to decrease in size, improvements to scale have spawned design implementation issues for some types of features, e.g., in CMOS ICs with features sized less than approximately twenty-two nanometers (nm). As IC technology continues to shrink, the growing need for empirical data from a design may exacerbate the uncertainty of the manufacturing process, thereby increasing the risk of defects or impaired operability. Conventional approaches for traversing physical limits may apply manual or computer-implemented techniques for increasing the resolution of chips printed using optical lithography. One such technique is known as optical proximity correction (OPC). OPC is a computational method for correcting irregularities and distortions arising from diffraction effects by the transforming of mask geometries.
Conventional OPC approaches can use empirical approximation models, which must be calibrated by fitting the model to an existing group of portions within an IC layout, also known as clips. This group of clips can be known as a sample plan. Conventionally, the clips of the sample plan are chosen by application of several constraints, including aerial image-based constraints known as image parameters, which may define a minimum intensity, a maximum intensity, a slope, and a curvature, or a critical dimension (CD), such as the minimum space between printed shapes or width of a printable shape.
The quality of OPC modeling may depend on a user's success in selecting a sample plan from hundreds of thousands of clips, and compiling the sample plan as a test mask layout. Experts typically calibrate conventional OPC models. These experts can calibrate each model by choosing or adjusting the contents of the sample plan based on previous implementations and empirical data relevant to the present sample plan. However, this process greatly increases in complexity as advances in lithography demand smaller transistor sizes. In addition, pressure to deliver a product within time constraints may prohibit the manual building or adjusting of a sample plan. Existing automatic or semiautomatic approaches to select a sample plan are generally limited to selecting a small sample from a very large initial set of clips and/or manually defining at least a minimal size (i.e., number of clips) in a sample plan for a particular IC layout.